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The integration of LLMs into EDA workflows could significantly amplify hardware vulnerabilities, but innovative defenses like split manufacturing may offer a pathway to secure chiplet systems.
LLMs can generate hardware designs that are functionally correct but often lag in timing performance, revealing a complex trade-off in financial FPGA design.
Gradient leakage attacks can reveal critical circuit information, exposing GNNs to significant security risks that current defenses struggle to mitigate effectively.
Standardized, modular GenAI teaching units in GUIDE offer a practical path to integrating cutting-edge AI tools into digital design education.
LLMs generating hardware code often fail *after* synthesis, and the type of failure (elaboration errors vs. missing wrappers) systematically depends on whether the model is proprietary or open-weight.
