Shreejith Shanker

FINNAS is presented, a FINN-guided hardware-aware evolutionary neural architecture search framework that jointly searches quantised MLP depth, width, and global precision settings, and ranks candidates using proxy validation accuracy together with FINN-estimated LUT usage and latency under a fully parallel mapping.

This paper proposes an Efficient Broad Learning (EBL) framework for distributed adaptive harmonic estimation, a quantised FPGA acceleration framework for BLS-style harmonic estimation that offers high-accuracy estimation with half-cycle input, reconfigurable flexibility enabled by the FPGA implementation, and ultra-low latency.

This work presents a machine learning-based IDS implemented within an FPGA-based SmartNIC pipeline, integrating P4-based packet parsing with a LogicNets IDS model implemented in RTL, enabling deterministic, low-latency inference.

Achieving a 20.58x reduction in search cost for optimal neural network configurations on FPGAs could revolutionize resource-efficient AI deployment at the edge.

A novel duty cycle predictive MPCC reduces current harmonics in EV charging by over 75%, tackling a critical grid integration challenge.