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This paper proposes an Efficient Broad Learning (EBL) framework for distributed adaptive harmonic estimation, a quantised FPGA acceleration framework for BLS-style harmonic estimation that offers high-accuracy estimation with half-cycle input, reconfigurable flexibility enabled by the FPGA implementation, and ultra-low latency.
This work presents a machine learning-based IDS implemented within an FPGA-based SmartNIC pipeline, integrating P4-based packet parsing with a LogicNets IDS model implemented in RTL, enabling deterministic, low-latency inference.