Yan Tan

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Code Generation & Program Synthesis (2)Eval Frameworks & Benchmarks (2)Data Curation & Synthetic Data (1)

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Yangdi Lyu (2)Tong Liu (1)Xiangchen Meng (1)Xiangchen Meng (1)

Papers (2)

Apr 20, 2026

Yan Tan +3Apr 20, 2026

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation

LLMs can now generate Verilog code with significantly higher compilation success and functional correctness, outperforming specialized and commercial tools, thanks to a novel contrastive learning approach.

Yan Tan, Tong Liu, Xiangchen Meng +1

Code Generation & Program Synthesis Data Curation & Synthetic Data Eval Frameworks & Benchmarks

Mar 12, 2026

AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning

LLMs can now generate Verilog RTL code with over 80% functional correctness and 25% less redundant logic, thanks to a novel framework that combines semantic reasoning with state-space exploration.

Yan Tan, Xiangchen Meng, Zijun Jiang +1

Code Generation & Program Synthesis Eval Frameworks & Benchmarks

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Yan Tan

Research focus

Frequent co-authors

Papers (2)