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LLMs can now write better hardware verification code: CoverAssert boosts functional coverage by up to 15% by iteratively guiding LLMs with coverage feedback.
Unlock better hardware designs: RTLSeek's diversity-oriented RL lets LLMs explore a wider range of Verilog implementations, boosting both correctness and design options.
Pecker pinpoints hardware bugs in sequential designs with significantly higher accuracy (up to 85% within Top-5 ranks) by untangling the temporal mess of error propagation that confounds existing techniques.
LLMs can now generate significantly better SystemVerilog assertions by iteratively refining their outputs based on functional coverage feedback, boosting branch, statement, and toggle coverage by up to 15.69%.
