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CoverAssert is introduced, an iterative framework that leverages LLMs to generate SystemVerilog assertions (SVAs) from natural language specifications while maximizing functional coverage. It clusters assertions based on semantic and AST-based structural features, maps them to specifications, and uses coverage feedback to guide the LLM in prioritizing uncovered areas. Experiments demonstrate that CoverAssert, when integrated with existing tools, significantly improves branch, statement, and toggle coverage in open-source designs.
LLMs can now write better hardware verification code: CoverAssert boosts functional coverage by up to 15% by iteratively guiding LLMs with coverage feedback.
LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.
