Johann Knechtel

The integration of LLMs into EDA workflows could significantly amplify hardware vulnerabilities, but innovative defenses like split manufacturing may offer a pathway to secure chiplet systems.

LLMs can generate hardware designs that are functionally correct but often lag in timing performance, revealing a complex trade-off in financial FPGA design.

Gradient leakage attacks can reveal critical circuit information, exposing GNNs to significant security risks that current defenses struggle to mitigate effectively.