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This paper introduces a hardware co-design law for on-device LLMs that models training loss as a function of architectural hyperparameters and characterizes inference latency using roofline modeling. They trained 170 models on NVIDIA Jetson Orin, fitting a scaling law relating architecture to training loss and coupling it with latency modeling to establish an accuracy-latency correspondence. The approach identifies Pareto-optimal architectures, reducing architecture selection time and achieving a 19.42% perplexity reduction compared to Qwen2.5-0.5B at the same latency.
Forget months of architecture search: this hardware co-design framework slashes the time to days and beats Qwen2.5-0.5B's perplexity by 19% at the same latency on NVIDIA Jetson Orin.
Vision-Language-Action Models (VLAs) have emerged as a key paradigm of Physical AI and are increasingly deployed in autonomous vehicles, robots, and smart spaces. In these resource-constrained on-device settings, selecting an appropriate large language model (LLM) backbone is a critical challenge: models must balance accuracy with strict inference latency and hardware efficiency constraints. This makes hardware-software co-design a game-changing requirement for on-device LLM deployment, where each hardware platform demands a tailored architectural solution. We propose a hardware co-design law that jointly captures model accuracy and inference performance. Specifically, we model training loss as an explicit function of architectural hyperparameters and characterise inference latency via roofline modelling. We empirically evaluate 1,942 candidate architectures on NVIDIA Jetson Orin, training 170 selected models for 10B tokens each to fit a scaling law relating architecture to training loss. By coupling this scaling law with latency modelling, we establish a direct accuracy-latency correspondence and identify the Pareto frontier for hardware co-designed LLMs. We further formulate architecture search as a joint optimisation over precision and performance, deriving feasible design regions under industrial hardware and application budgets. Our approach reduces architecture selection from months to days. At the same latency as Qwen2.5-0.5B on the target hardware, our co-designed architecture achieves 19.42% lower perplexity on WikiText-2. To our knowledge, this is the first principled and operational framework for hardware co-design scaling laws in on-device LLM deployment. We will make the code and related checkpoints publicly available.
