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The paper introduces MING, an MLIR-based framework for automating the HLS design process of CNNs targeting resource-constrained edge FPGAs. MING employs a streaming architecture with optimized buffer management to address the limitations of existing frameworks in handling stringent resource constraints. Experiments demonstrate that MING achieves significant speedups (15x for multi-layer CNN kernels and up to 200x for single-layer kernels) and can generate efficient designs for larger input sizes where other frameworks fail.
Edge CNNs get a 15-200x speed boost thanks to MING, a new MLIR-based HLS framework that cleverly manages resources on FPGAs.
Driven by the increasing demand for low-latency and real-time processing, machine learning applications are steadily migrating toward edge computing platforms, where Field-Programmable Gate Arrays (FPGAs) are widely adopted for their energy efficiency compared to CPUs and GPUs. To generate high-performance and low-power FPGA designs, several frameworks built upon High Level Synthesis (HLS) vendor tools have been proposed, among which MLIR-based frameworks are gaining significant traction due to their extensibility and ease of use. However, existing state-of-the-art frameworks often overlook the stringent resource constraints of edge devices. To address this limitation, we propose MING, an Multi-Level Intermediate Representation (MLIR)-based framework that abstracts and automates the HLS design process. Within this framework, we adopt a streaming architecture with carefully managed buffers, specifically designed to handle resource constraints while ensuring low-latency. In comparison with recent frameworks, our approach achieves on average 15x speedup for standard Convolutional Neural Network (CNN) kernels with up to four layers, and up to 200x for single-layer kernels. For kernels with larger input sizes, MING is capable of generating efficient designs that respect hardware resource constraints, whereas state-of-the-art frameworks struggle to meet.