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This paper introduces a piecewise linear (PWL) interpolation framework utilizing partial reconfiguration in FPGAs to efficiently implement non-linear functions like exponential and sigmoid, which are critical for AI and LLM acceleration. By separating the architecture into static and reconfigurable regions, the authors demonstrate that non-uniform segmentation enhances accuracy in high-curvature areas while uniform segmentation minimizes hardware overhead. The proposed method achieved up to 43% reduction in LUTs and 50% in flip-flops and other resources compared to a static design, showcasing a viable strategy for optimizing area-latency trade-offs in FPGA implementations for LLMs.
Non-uniform segmentation in FPGA-based non-linear function interpolation can significantly boost accuracy while slashing hardware costs by up to 50%.
Non-linear functions such as exponential and sigmoid are essential in AI and LLM acceleration, although implementing them efficiently on FPGAs is still costly. This paper proposes a PWL interpolation framework based on partial reconfiguration to reduce hardware cost while preserving flexibility. The architecture separates the design into a static region for communication and control, and a reconfigurable region where different interpolation modules can be dynamically loaded. Uniform and non-uniform segmentation strategies are evaluated for exponential and sigmoid functions using FP16 and FP32 arithmetic. Results show that non-uniform segmentation can improve accuracy in high-curvature regions, while uniform segmentation offers lower hardware overhead. At the system level, the reconfigurable implementation achieved significant area savings, reaching up to 43\% less LUTs, 50\% less flip-flops, BRAMs and DSPs cells, compared against a static design containing both operators; all this with predictable reconfiguration latency. These results show that partial reconfiguration is a practical approach for exploring area-latency trade-offs in FPGA-based acceleration of non-linear functions for LLM workloads.