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This paper introduces Dryas, an open-source tool designed for high-speed interconnect tracing and analysis, specifically targeting FPGA-based implementations. By leveraging a run-time reprogrammable overlay engine that utilizes non-deterministic finite automata (NFAs), Dryas can efficiently filter and inspect complex events at a cache-line granularity without interrupting ongoing operations. The results demonstrate that Dryas significantly reduces the time and complexity involved in debugging and optimizing interconnects, showcasing its scalability and effectiveness through practical use cases.
Dryas can dynamically adjust its filtering capabilities in under a second, revolutionizing how engineers debug and analyze high-speed interconnects without interrupting their operation.
The proliferation of heterogeneous components in modern computing systems has been accompanied by new higher bandwidth and lower latency interconnects. These interfaces and protocols are enormously complex and the process of developing, debugging, and analyzing FPGA-based implementations requires significant engineering work. Moreover, once a functional implementation is completed, optimization of the controller and associated software requires processing potentially hundreds of gigabytes of trace data. In this paper, we present Dryas, an open source tool for analyzing such an interconnect. We developed our tool, using minimal hardware resources, alongside an FPGA implementation of a very high speed, low latency (30~GiB/s, 200~ns) interconnect. With our run-time reprogrammable overlay engine we can inspect this interconnect to find rare, complex, or transient events even at full operation. This filtering engine is based on non-deterministic finite automata (NFAs), efficiently implemented using state transition elements (STEs), allowing us to trace events at a cache-line granularity. Moreover we can change the filters in less than a second, without reprogramming the FPGA or interfering with the running application. This data enables not only debugging the implementation of the interconnect itself, but analyzing the behavior of accelerated applications. We examine the mathematical basis for using NFAs and describe their implementation on a real coherent CPU-FPGA research platform. We then evaluate the scalability of Dryas for various size NFAs, followed by two different use cases: debugging FPGA implementation of the interconnect and analyzing cache behavior.
