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This paper analyzes the impact of FPGA-based Time-to-Digital Converter (TDC) nonlinearity on Quantum Key Distribution (QKD) system performance, specifically its effect on coincidence timing, accidental-coincidence rate, and Quantum Bit Error Rate (QBER). They develop a system-level model combining random timing uncertainty and deterministic nonlinearity to understand this propagation. The authors then propose fabric-level mitigation strategies using LUT-assisted delay shaping and placement constraints, demonstrating a 14%-21% reduction in integral nonlinearity (INL) and a corresponding improvement in estimated secret fraction.
Uncorrected nonlinearity in FPGA-based time-to-digital converters can significantly degrade QKD security, demanding explicit consideration beyond mere calibration.
Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.
