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This paper introduces CLIPGen, a framework for automated generation of chiplet link IP models tailored for 2.5D system-in-package architectures. CLIPGen bridges the gap between detailed and high-level models by providing power, performance, and area estimates alongside standard design collaterals (Verilog, Liberty, LEF, datasheet) for various packaging and communication configurations. A case study using generated UCIe interfaces demonstrates the framework's utility in co-optimizing package and chiplet architecture.
Stop hand-waving 2.5D interconnect: CLIPGen auto-generates detailed chiplet link IP models, letting you explore power, performance, and area tradeoffs across packaging options *before* committing to silicon.
Advanced 2.5D Systems-in-Package (SiPs) compose a growing portion of high-performance systems. While the packaging and interconnect choices play a large role in the overall system design, system architects still lack a suitable framework for early design space exploration which takes these choices into account. Current interconnect models fall mostly into the categories of 1) detailed models which are generally inflexible and require deep packaging expertise, or 2) high-level models which don't provide enough information to make accurate architectural design decisions. In this work, we present an automated chiplet IP generation framework which provides power, performance, and area estimates for various 2.5D packaging and communication configurations. The IP generator produces standard collaterals required for high-level simulation/estimation, RTL simulation, and place-and-route-level implementation (Verilog, Liberty, LEF, and datasheet). Using our framework, architects can co-optimize the package and chiplet architecture through rapid power, performance, and area estimates of various packaging strategies. As a case study, we examine generated UCIe interfaces across several packaging options.
