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The Memory-Centric Hierarchical Architecture (MCHA) addresses the limitations of conventional computing architectures in handling parallel-sequential workloads, such as Multi-Agent Reinforcement Learning (MARL) and probabilistic graphical models, by implementing a hierarchical communication strategy that reduces global memory bandwidth demands. MCHA's innovative parallel-sequential programming model employs event-driven conditional triggers to minimize data transmission latency, resulting in substantial performance improvements. Benchmarks reveal that MCHA achieves speedups of 153.06脳 to 2456.96脳 over NVIDIA A100 GPUs on MARL tasks while significantly decreasing main memory access from 96% to 5.44%.
MCHA achieves unprecedented performance speedups for parallel-sequential computing tasks, outperforming NVIDIA A100 GPUs by up to 2456.96脳.
Emerging workloads, such as Multi-Agent Reinforcement Learning (MARL), large-scale neuromorphic computing, and probabilistic graphical models, intrinsically exhibit parallel-sequential computing patterns. While these tasks demand massive parallelism to achieve high throughput, they are severely bottlenecked by irregular data access patterns centralized to main memory. Consequently, conventional architectures face fundamental limitations when executing these workloads, primarily manifesting as global buffer saturation and memory-bound bottlenecks. To address these challenges, we propose the Memory-Centric Hierarchical Architecture (MCHA), a reconfigurable hardware solution tailored for parallel-sequential execution. MCHA leverages a hierarchical communication strategy that facilitates distributed, inter-core data routing, thereby significantly reducing the bandwidth burden on the global memory. Complementing the hardware, MCHA introduces a novel parallel-sequential programming model that utilizes event-driven conditional triggers to effectively hide data transmission latency within the execution pipeline. We benchmark MCHA against a diverse suite of parallel-sequential tasks, including MARL, motor variable control, and Markov random fields. Validated through our open-source, cycle-accurate simulator, MCHA demonstrates performance speedups ranging from 153.06$\times$ to 2456.96$\times$ over NVIDIA A100 GPUs on MARL workloads, while maintaining robust programming flexibility across other application domains. Furthermore, the architecture successfully reduces main memory access from 96% to 5.44%. When synthesized in a 28 nm process, the MCHA implementation occupies an area footprint of 2.92mm$^2$ and consumes 115.36 mW of power at 200 MHz. MCHA is open-sourced at https://github.com/carabdis/MCHA.
