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This paper introduces PowerScope, the first machine learning-based framework for intra-cycle power estimation that operates directly on RTL simulation traces, bypassing the need for computationally intensive post-layout gate-level simulations. By leveraging this approach, PowerScope achieves a median absolute percentage error of 5.88% and a mean error of 9%, while significantly accelerating the estimation process by approximately 80 times compared to traditional methods. The framework's predictions are also validated for use in pre-silicon power side-channel leakage assessments, showcasing its practical applicability in design workflows.
PowerScope achieves intra-cycle power estimation with 80x speedup and competitive accuracy, revolutionizing power analysis workflows.
Power estimation at sub-clock-cycle temporal resolutions is critical for tasks such as power delivery network (PDN) design, dynamic voltage droop analysis, and pre-silicon power side-channel security evaluation. Designers commonly rely on commercial post-layout gate-level power analysis tools for these tasks, but these flows are computationally expensive and scale poorly with design size and workload length. Machine learning (ML)-based power estimation frameworks have shown promise in accelerating power estimation, but prior efforts only address average power or per-cycle power estimation. We propose PowerScope, the first ML-based intra-cycle power estimation framework. PowerScope operates purely on RTL simulation traces at inference time, eliminating the need for post-layout gate-level simulation and power analysis per workload. Across a diverse benchmark suite, PowerScope achieves 5.88% median and 9% mean absolute percentage error compared to commercial post-layout gate-level power estimates while running ~80x faster. We further demonstrate that PowerScope's predictions can be reliably used for the downstream task of pre-silicon power side-channel leakage assessment.
