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This paper introduces PIP-NTT, a novel memory-parallelized accelerator designed to enhance the efficiency of iterative number theoretic transforms (NTT) crucial for lattice-based post-quantum cryptography. By employing a strategy that utilizes four smaller n/4-sized memories and a multiplication-free rescaling architecture, the authors significantly improve computational throughput while maintaining a compact memory footprint. Experimental evaluations on FPGA platforms demonstrate that PIP-NTT achieves up to 2.67x higher efficiency in Area-Time Product compared to existing NTT accelerators, highlighting its potential for scalable cryptographic hardware solutions.
Achieving 2.67x higher efficiency in NTT computations could redefine performance benchmarks for post-quantum cryptographic hardware.
The iterative forward and inverse number theoretic transform (NTT) is a key component in lattice-based post-quantum cryptography (PQC), typically implemented using Cooley-Tukey and Gentleman-Sande butterfly units. Existing iterative NTT accelerators often rely on ping-pong memory schemes and large memory blocks tied to the cyclotomic ring, which limits overall efficiency. To overcome this, we propose a memory-parallelization strategy using four smaller n/4-sized memories for ring size n, preserving the total memory footprint of conventional designs. We also introduce a multiplication-free rescaling architecture for the inverse NTT. Building on these innovations, we perform a comprehensive hardware-based design space exploration of unified Cooley-Tukey and Gentleman-Sande butterfly units, evaluating both coarse- and fine-grained pipelining strategies. The resulting optimized butterfly unit forms the core of our proposed pipelined and memory-parallelized NTT accelerator,"PIP-NTT". It integrates two such units alongside the memory-parallelization scheme to boost computational throughput under tight area constraints. Experimental results on FPGA platforms show that PIP-NTT achieves 2.67x and 1.48x higher efficiency in average Area-Time Product compared to the most area-optimized and high-speed NTT accelerators in the literature. The design is scalable across butterfly radices and adaptable to other PQC schemes, making it a versatile solution for future cryptographic hardware
