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The paper introduces ChipBench, a new benchmark designed to evaluate LLMs on AI-aided chip design tasks, specifically Verilog generation, debugging, and reference model generation. The benchmark includes 44 complex modules, 89 debugging cases, and 132 reference model samples across multiple languages, aiming to address the limitations of existing saturated benchmarks. Experiments using ChipBench reveal that even state-of-the-art LLMs like Claude-4.5-opus exhibit significant performance gaps, achieving only 30.74% and 13.33% on Verilog and Python reference model generation, respectively, highlighting the need for further research.
LLMs still have a long way to go in AI-aided chip design, with even the best models achieving surprisingly low scores on the new ChipBench benchmark for Verilog generation and reference model creation.
While Large Language Models (LLMs) show significant potential in hardware engineering, current benchmarks suffer from saturation and limited task diversity, failing to reflect LLMs'performance in real industrial workflows. To address this gap, we propose a comprehensive benchmark for AI-aided chip design that rigorously evaluates LLMs across three critical tasks: Verilog generation, debugging, and reference model generation. Our benchmark features 44 realistic modules with complex hierarchical structures, 89 systematic debugging cases, and 132 reference model samples across Python, SystemC, and CXXRTL. Evaluation results reveal substantial performance gaps, with state-of-the-art Claude-4.5-opus achieving only 30.74\% on Verilog generation and 13.33\% on Python reference model generation, demonstrating significant challenges compared to existing saturated benchmarks where SOTA models achieve over 95\% pass rates. Additionally, to help enhance LLM reference model generation, we provide an automated toolbox for high-quality training data generation, facilitating future research in this underexplored domain. Our code is available at https://github.com/zhongkaiyu/ChipBench.git.
Stanford HAI