Search papers, labs, and topics across Lattice.
This paper introduces Jiao, a novel architecture for mixed-criticality robotics systems aiming to bridge the gap between safety-critical control and user customization on shared multicore platforms. Jiao employs a Safe IO Cell for hardware-level overrides, a Parameter Synchronization Service to manage cross-domain complexity, and a Safety Communication Layer for IEC 61508-aligned verification. Empirical evaluation on an ARM Cortex-A55 platform shows Jiao reduces cycle-period jitter by 84.5% and significantly decreases tail timing error, demonstrating improved isolation and real-time performance.
Achieve near order-of-magnitude reduction in tail timing error in mixed-criticality robotics by decoupling safety-critical control from user applications.
Consumer robotics demands consolidation of safety-critical control, perception pipelines, and user applications on shared multicore platforms. While static partitioning hypervisors provide hardware-enforced isolation, directly transplanting automotive architectures encounters an expertise asymmetry problem in which end-users modifying robot behavior lack the systems knowledge that platform developers possess. We present an architecture addressing this challenge through three integrated components. A Safe IO Cell provides hardware-level override capability. A Parameter Synchronization Service encapsulates cross-domain complexity. A Safety Communication Layer implements IEC~61508-aligned verification. Our empirical evaluation on an ARM Cortex-A55 platform demonstrates that partition isolation reduces cycle-period jitter by 84.5\% and cuts tail timing error by nearly an order of magnitude (p99 $|$jitter$|$ from 69.0\,$\mu$s to 7.8\,$\mu$s), eliminating all $>$50\,$\mu$s~excursions.
