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This paper introduces Assertain, an automated framework using LLMs to generate SystemVerilog Assertions for hardware security verification by integrating RTL design analysis, CWE mapping, and threat model intelligence. A self-reflection refinement mechanism is used to improve the syntactic correctness and semantic consistency of the generated assertions. Experiments on 11 hardware designs show that Assertain outperforms GPT-5 in correct assertion generation, CWE coverage, and architectural flaw detection by 61.22%, 59.49%, and 67.92%, respectively.
LLMs can now automatically generate security assertions for hardware designs, outperforming even GPT-5 by a large margin.
The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property verification. This paper presents Assertain, an automated framework that integrates RTL design analysis, Common Weakness Enumeration (CWE) mapping, and threat model intelligence to automatically generate security properties and executable SystemVerilog Assertions. Assertain leverages large language models with a self-reflection refinement mechanism to ensure both syntactic correctness and semantic consistency. Evaluated on 11 representative hardware designs, Assertain outperforms GPT-5 by 61.22%, 59.49%, and 67.92% in correct assertion generation, unique CWE coverage, and architectural flaw detection, respectively. These results demonstrate that Assertain significantly expands vulnerability coverage, improves assertion quality, and reduces manual effort in hardware security verification.
