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This paper introduces LevelSyn, a physical-aware logic synthesis framework that utilizes a level-asynchronous Graph Neural Network (GNN) to enhance the integration of logic synthesis with physical design, addressing the limitations of traditional Wire Load Models. By employing hierarchical representation learning and a wirelength-driven optimization engine, LevelSyn achieves significant improvements in power and timing performance while effectively managing memory constraints through a level-aligned subgraph partitioning strategy. Experimental results indicate that LevelSyn outperforms state-of-the-art methods, achieving an average power reduction of 6.89% and a timing delay improvement of 27.48%, along with a dramatic reduction in design rule check violations.
LevelSyn achieves a remarkable 6.89% power reduction and 27.48% timing improvement by integrating physical awareness into logic synthesis, revolutionizing design closure efficiency.
As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design closure cycles. Traditional logic synthesis relies on non-physical Wire Load Models (WLMs), while recent spectral-based placement predictors often neglect the inherent hierarchical logic depth and signal flow of netlists, which leads to low-fidelity spatial estimations. To bridge this gap, we propose LevelSyn, a novel physical-aware logic synthesis framework that integrates hierarchical representation learning with a wirelength-driven optimization engine. At its core, LevelSyn leverages a level-asynchronous Graph Neural Network (GNN) to predict high-fidelity gate coordinates by capturing the structural and directional semantics of And-Inverter Graphs (AIGs). To handle industrial-scale designs, a level-aligned subgraph partitioning strategy is introduced to eliminate memory bottlenecks while preserving local logical dependencies. These spatial insights are seamlessly integrated into a newly developed physical-informed synthesis engine within the Berkeley ABC framework. Experimental results on the EPFL benchmark suite demonstrate that LevelSyn significantly outperforms state-of-the-art (SOTA) methods, achieving an average power reduction of 6.89\% and a timing delay improvement of 27.48\%. Furthermore, post-place-and-route validation shows a 99.59\% reduction in design rule check (DRC) violations, highlighting its effectiveness in accelerating design convergence.
