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This paper introduces EXPLORE, a novel framework that combines simulator-guided Monte Carlo Tree Search (MCTS) with transformer-based decoding to enhance the generation of analog circuit topologies. By strategically directing the simulator budget towards topology-altering decisions and utilizing language-model priors, EXPLORE significantly improves the success rate of circuit design from 12% to 65% on a challenging benchmark. These advancements not only demonstrate the efficacy of integrating structured search with language models but also pave the way for scalable design automation in analog circuits.
EXPLORE boosts analog circuit topology generation success rates from 12% to 65% by intelligently combining Monte Carlo Tree Search with transformer decoding.
Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands. Recent advances have applied sequence-to-sequence fine-tuning on pretrained language models to directly generate circuit topologies from user specifications in a single pass. However, these one-shot generation methods failed to generate complex circuits due to their exponentially growing search spaces and limited training datasets. In this paper, we present EXPLORE, a search-enhanced framework that integrates simulator-guided Monte Carlo Tree Search (MCTS) with transformer-based decoding to enable test-time scaling for analog topology generation. By leveraging language-model priors and bypassing high-confidence structural tokens, EXPLORE allocates expensive simulator budget primarily toward topology-altering decisions during search. On a 6-component benchmark at a tight tolerance of 0.01, EXPLORE raises the success rate from 12% for one-shot generation and 33% for a sampling-and-filter baseline to 65%, and lowers MSE by over 20% relative to sampling-and-filter under the same search budget. These results establish EXPLORE as the first framework to integrate structured test-time search with LM decoding for analog topology generation, and a practical step toward scaling LLM-driven design automation.
