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UVMarvel automates UVM testbench generation for subsystem-level RTL verification by using LLMs to translate specifications into protocol-correct testbenches. It introduces an Intermediate Representation (IR) and Bus Protocol Library for specification translation, along with a Signal Tracker and Verilog Patching Library to refine LLM-generated stimuli. The framework achieves 95.65% code coverage and reduces verification time to 4.5 hours, demonstrating the potential of LLMs in automating complex hardware verification tasks.
Automating UVM testbench generation with LLMs slashes verification time from days to hours, achieving near-complete code coverage.
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total effort. While the Universal Verification Methodology (UVM) improves reuse through structured verification environments, constructing subsystem-level UVM testbenches and generating high-quality stimuli still require extensive manual coding, repeated EDA tool runs, and deep protocol and micro-architectural expertise. We present UVMarvel, an automated verification framework that leverages Large Language Models (LLMs) to build UVM testbenches for subsystem-level RTL.UVMarvel introduces an Intermediate Representation (IR) and a Bus Protocol Library to translate heterogeneous specifications into protocol-correct subsystem-level UVM testbenches, and employs a Signal Tracker and a Verilog Patching Library to guide LLM-based stimuli refinement. UVMarvel is the first framework capable of automatically constructing subsystem-level UVM testbenches across mainstream bus protocols, and it achieves an average code coverage of 95.65%, while reducing verification time from several human working days to a 4.5-hour automated execution.
