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This paper introduces RAG-Enhanced Kernel-Based Heuristic Synthesis (RKHS), a novel methodology that leverages large language models (LLMs) to systematically synthesize reusable optimization heuristics for hardware design tasks such as placement, routing, and scheduling. By integrating retrieval-augmented generation with compact kernel heuristic templates and an iterative self-feedback refinement loop, the approach significantly enhances the efficiency of latency-minimizing list scheduling in high-level synthesis (HLS). The prototype achieves an 11% reduction in average schedule length compared to a baseline scheduler while maintaining a manageable runtime overhead of only 1.3 times.
LLMs can systematically generate effective hardware design heuristics, achieving an 11% reduction in scheduling latency with minimal overhead.
Heuristic design upholds modern electronic design automation (EDA) tools, yet crafting effective placement, routing, and scheduling strategies entails substantial expertise. We study how large language models (LLMs) can systematically synthesize reusable optimization heuristics beyond one-shot code generation. We propose RAG-Enhanced Kernel-Based Heuristic Synthesis (RKHS), which integrates retrieval-augmented generation (RAG), compact kernel heuristic templates, and an LLM-driven refinement loop inspired by iterative self-feedback. Applied to latency-minimizing list scheduling in high-level synthesis (HLS), a prototype reduces average schedule length by up to 11 percent over a baseline scheduler with only 1.3x runtime overhead, and the structured retrieval-synthesis loop generalizes to other EDA optimization problems.
