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This paper introduces VeriRefine, a novel approach that enhances the generation of synthesizable register-transfer-level (RTL) designs from natural language specifications by refining the specifications into explicit, schema-constrained representations before code generation. By employing per-signal Abstract Signal Transition Functions (ASTFs) and a comprehensive five-layer audit process, the method ensures that interpretation errors are addressed at the representation level, significantly improving the accuracy of the generated RTL code. The results demonstrate that VeriRefine achieves 94.0% functional correctness on RTLLM v2.0 and 98.1% on VerilogEval-Human v2, showcasing its effectiveness in mitigating understanding errors in RTL design generation.
Misinterpretations in RTL design generation can be fixed before code is even written, leading to a groundbreaking 94% functional correctness in generated designs.
Large language models can generate register-transfer-level (RTL) designs directly from natural language specifications. Their failures, however, arise mostly from understanding rather than coding \cite{zhang2026understanding, qiu2025towards}. A specification is informal and ambiguous, the model's interpretation stays implicit, and every misreading is committed silently into Verilog, where only simulation can expose it. Intermediate representations make the interpretation partly explicit, yet existing works don't verify the interpretation against the specification, and repair simulation failures at the code level regardless of where the misreading originated. VeriRefine instead treats specification refinement as a verifiable stage of RTL generation. It progressively refines the prose specification into an explicit, schema-constrained account of design intent, expressed as per-signal Abstract Signal Transition Functions (ASTFs) that commit each signal's logic style, clock domain, and reset behavior before any code exists and ground every behavior in a verbatim specification sentence. The refined specification then passes a five-layer audit spanning soundness, completeness, consistency, FSM integrity, and core RTL design rules, so interpretation errors are repaired at the representation level before any Verilog is generated. Once code is generated, each simulation failure is classified as an understanding error or a coding error and routed back to the corresponding stage for targeted repair. Because every signal's hardware class is fixed during refinement, synthesizability becomes a structural property of the pipeline rather than a post-hoc check. With Claude Sonnet 4.6, VeriRefine reaches 94.0\% functional correctness on RTLLM v2.0 and 98.1\% on VerilogEval-Human v2.
