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This paper provides a thorough evaluation of existing hardware fuzzing techniques across three abstraction layers: ISA, microarchitecture, and RTL, highlighting the distinct challenges and design trade-offs at each level. The authors identify critical gaps in current practices, such as the need for improved input generation and more effective feedback mechanisms, which hinder the efficacy of hardware verification. By proposing future research directions like hybrid fuzzing frameworks and AI-assisted test generation, the study aims to enhance the efficiency and reliability of hardware verification processes.
Current hardware fuzzing techniques are falling short, with significant gaps in input generation and feedback mechanisms that could undermine verification reliability.
This work presents a comprehensive analysis of contemporary hardware fuzzing techniques applied across three major abstraction layers: Instruction Set Architecture (ISA), microarchitecture, and Register-Transfer Level (RTL). Our study examines key factors including input stimulus quality, mutation strategies, feedback mechanisms, target platforms, reference models, and achieved coverage. We find challenges, goals, and design trade-offs vary significantly across abstraction layers. We further identify several unmet needs in current hardware fuzzing practices, such as intelligent input generation, reliable and scalable golden reference models, expressive feedback channels, and cross-layer integration. Building on these insights, we outline future research directions, including hybrid fuzzing frameworks, AI-assisted test generation, scalable reference models, standardized evaluation metrics and benchmarks, and human-in-the-loop automation for guided exploration and analysis. Together, they aim to unlock efficient, reliable, and comprehensive hardware verification solutions.
