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SymbolicLight V2 combines graded signed events, continuous-state processing, and softmax-free local attention into a 194M-parameter hybrid neuromorphic architecture targeting energy-efficient language inference. To convert model sparsity into real hardware savings, the authors implemented the architecture on an Alveo U50C FPGA and an ARM CPU using active-row weight gathering and sparse valid-state KV loading. The resulting FPGA deployment achieves a decode throughput of 643.2 tokens/s at 0.044 J per generated token鈥攁n 89.1% energy reduction compared to an RTX 5090 FP32 baseline鈥攚hile running at 65.4 tokens/s within a sub-10 W envelope on quad-core edge ARM silicon.
Event-driven neuromorphic execution slashes language model decode energy to 0.044 Joules per token by directly converting activation sparsity into skipped memory traffic rather than just idle compute cycles.
SymbolicLight V2 combines sparse event computation with continuous-state processing in a hybrid neuromorphic language architecture. Extending V1's spike-gated dual paths, it adds graded signed events at further projections and softmax-free local attention. We implement the 194M-parameter model on an Alveo U50C FPGA using digital fixed-point arithmetic and on an ARM CPU using sparse integer execution. Across three same-checkpoint FPGA implementations at 175 MHz, active-row weight gathering and valid-state KV loading raise decode throughput from 474.6 to 643.2 tokens/s for a 32-token prefix and 128 outputs. Estimated gross card energy falls from 0.06087 to 0.04407 J per generated token, a 27.6% reduction. Complete-request energy, including prefill, falls by 24.4-27.7% across three prefix lengths. An independent idle split attributes 82.8% of gross card energy to loaded idle, explaining the benefit of shorter token latency. Against the recorded RTX 5090 compiled-FP32 baseline, integer FPGA execution uses 89.1% less estimated card energy during short-context decode; arithmetic precisions differ, and the GPU baseline is not the lowest-energy tested configuration. On four Cortex-A76 cores of a ROCK 5T, complete requests reach 65.4 tokens/s at 9.80 W and 0.151 J per generated token at the adapter's AC input. These results connect event sparsity to omitted computation and data movement. The mechanisms also support other dedicated V2 implementations: increasing throughput by a greater factor than active power lowers energy per generated token. Evaluation holds the deployed checkpoint fixed; its quality trails a same-budget dense control, so the results do not establish equal-quality efficiency.
