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This paper investigates the retention loss in 65 nm single-poly floating-gate analog in-memory computing and its detrimental effects on inference accuracy. By implementing circuit-level compensation techniques alongside batch normalization recalibration, the authors demonstrate that it is possible to recover inference accuracy within 2-4% of baseline levels even after 60 days of programming. The findings are validated through experiments and simulations on neural network models, highlighting a practical approach to enhance the reliability of analog memory systems in AI applications.
Retention loss doesn't have to mean accuracy loss; innovative compensation techniques can recover nearly all inference performance even after prolonged storage.
We show with experiments and system-level simulations that it is possible to successfully mitigate the impact of retention loss on inference accuracy degradation by using both circuit-level compensation techniques and batch normalization recalibration at the algorithmic level. Experiments are performed on a single-poly floating-gate (FG) analog non-volatile memory array for analog in-memory computing fabricated in a standard 65 nm CMOS. We use a model of retention-loss statistics calibrated with experiments to evaluate the system-level impact on neural network models such as VGG-10/CIFAR-10 and WideResNet-28-10/CIFAR-100. We show that, after 60 days since programming, combined mitigation techniques enable to recover the baseline inference accuracy within 2-4%
