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This paper introduces a novel low-power circuit-switched Network-on-Chip (NoC) design leveraging Spatial Division Multiplexing (SDM) to exploit predictable inter-core traffic patterns in AI chips. The design combines hard-wired switches with programmable crossbars in a new router architecture, optimized by a task mapping and route assignment algorithm. Results demonstrate a 38% reduction in NoC power consumption, 19% smaller area, and 12% lower packet latency compared to conventional packet-switched NoCs.
Radically reduce power consumption in AI chips with a circuit-switched network-on-chip that carves out dedicated "lanes" for predictable communication flows.
In many modern AI chips and multicore systems-on-chip, embedded applications exhibit predictable inter-core traffic behavior that can be characterized at design time. For such applications, a variety of design-time traffic management and network optimization techniques can be employed to improve NoC power and performance. To exploit this predictability, we propose a novel low-power circuit-switched NoC design. It uses the Spatial Division Multiplexing (SDM) technique to establish circuits, implemented as subsets of NoC wires, for the communication flows of a target application. To further reduce the power profile of SDM, the design incorporates a new router architecture that combines hard-wired switches with conventional programmable crossbars. The architecture is complemented by an algorithm that maps application tasks onto a mesh NoC and assigns an SDM route with adequate bit-width to each circuit built for inter-task communication flows. Compared with a conventional packet-switched NoC, the proposed approach achieves approximately 38% lower NoC power consumption, 19% smaller area, and 12% lower packet latency.
