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CXLRAMSim is introduced as a novel full-system simulator integrated with gem5, designed for high-fidelity modeling of CXL-based memory expansion in LLM-centric systems. By simulating CXL devices on the I/O bus, CXLRAMSim enables the use of unmodified Linux kernels and realistic memory access patterns, overcoming limitations of existing tools. The simulator accurately captures cache pollution effects and provides detailed CXL.mem characterization.
Finally, a gem5-integrated simulator that accurately models CXL memory expansion for LLMs, capturing real-world effects like cache pollution.
The growing demands in the training and inference of Large Language Models (LLMs) are accelerating the adoption of scale-up systems that extend server shared memory through the use of Compute Express Link (CXL)-based load/store interconnects. Accurate full-system simulation of such architectures remains challenging, as existing tools (all very recent) rely on simplified or non-compliant architectural models, impacting accuracy and usability. We present CXLRAMSim, the first gem5-integrated, full-system simulator that models CXL devices at their correct position on the I/O bus, enabling the use of unmodified Linux kernels and software stack, realistic latency-bandwidth behavior and true interleaving with system DRAM. Our approach provides high-fidelity CXL.mem characterization and captures key challenges such as cache pollution when accessing CXL memory.
