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This paper details an advanced Performance Verification (PV) methodology implemented across four generations of the AmpereOne CPU core, emphasizing the importance of pre-silicon verification in the face of slowed process technology scaling. The approach leverages cycle-accurate correlation between RTL design and a trace-driven performance model, incorporating data-driven workload curation and a high-frequency regression system. Case studies on the Branch Prediction Unit and L2 Prefetcher illustrate how this iterative and hierarchical strategy effectively mitigates the risk of post-silicon bugs while ensuring performance targets are met.
A disciplined, iterative verification process can prevent costly post-silicon bugs and ensure complex processors hit performance targets.
As process technology scaling slows, microarchitectural innovation has become the primary driver of performance gains, making pre-silicon Performance Verification (PV) more critical than ever. This paper presents the industrial-scale PV methodology applied across four generations of the AmpereOne custom CPU core, centered on the cycle-accurate correlation of the RTL design against a trace-driven performance model. The methodology integrates data-driven workload curation, a high-frequency daily regression system, and a unified event-stream framework for analysis. We demonstrate this methodology through case studies of the Branch Prediction Unit and L2 Prefetcher, highlighting a hierarchical strategy that first isolates individual units for focused correlation before proceeding to full-core verification. The results demonstrate that this disciplined, iterative process is indispensable for avoiding costly post-silicon bugs and ensuring complex processors meet their performance targets. We end with a look towards the future of PV in the microprocessor industry.
