Search papers, labs, and topics across Lattice.
This paper evaluates distributed quantum circuit partitioning algorithms by applying established monolithic benchmarking metrics to assess the performance impacts of network constraints. It highlights that while partitioning algorithms may have similar entanglement costs, they can lead to significantly different physical execution penalties, such as increased circuit depth and reduced gate density. The findings underscore the necessity of comprehensive circuit-level metrics for the effective design of DQC compilers, addressing a critical gap in current evaluation methods.
Partitioning algorithms with similar entanglement costs can incur drastically different execution penalties, revealing hidden trade-offs that could reshape DQC compiler design.
Distributed Quantum Computing (DQC) addresses the physical scaling limitations of monolithic quantum processors by networking modular Quantum Processing Units (QPUs). Efficient execution of quantum algorithms on DQC architectures requires compiling them across QPUs while minimizing inter-QPU communication bottlenecks, primarily through circuit partitioning. However, current evaluations of state-of-the-art partitioning heuristics focus primarily on the total entanglement cost of the partitions, failing to capture the broader structural and temporal overheads introduced by distributed network constraints. This paper addresses this evaluation gap by applying established monolithic benchmarking metrics to partitioned distributed circuits to quantify the performance impact of network constraints. Using an open-source, automated evaluation pipeline, we systematically assess diverse partitioning algorithms across standardized workloads and quantum network topologies. Our empirical results reveal that partitioning algorithms with comparable entanglement costs can still introduce drastically different physical execution penalties. By exposing these hidden trade-offs, such as severe increases in circuit depth and substantial reductions in gate density, this study demonstrates that comprehensive circuit-level metrics are essential for guiding the future design of DQC compilers.
