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The authors developed Backline, an MLIR-based compiler and runtime within PennyLane and Catalyst that lowers high-level Python code into heterogeneous execution across distributed CPUs, GPUs, and FPGAs. This bridges the critical engineering gap between flexible, high-level quantum algorithm development and the sub-microsecond latency thresholds demanded by real-time quantum error correction. Controlling execution via an AMD VPK120 FPGA over RoCE v2, the framework achieved steady-state median round-trip latencies of 2.305 碌s to an AMD Threadripper CPU and 4.5 碌s to an AMD MI210 GPU across one million rounds.
Sub-5-microsecond hybrid execution across CPUs, GPUs, and FPGAs is now achievable directly from pure Python, removing the rigid manual hardware-programming bottleneck currently stalling real-time quantum error correction.
Moving from quantum research and development to production-grade, fault-tolerant quantum workload execution remains one of the most significant challenges facing quantum platform builders. While Python frameworks have enabled an easy entry point for quantum algorithm design, the low-latency requirements for real-time quantum error correction (QEC) demand performance that traditional interpreted environments cannot provide. FPGAs and ASICs play a central role at these layers, but their specialized programming models make development rigid and time-consuming. CPUs, GPUs, and other accelerators introduce a different challenge: as infrastructure becomes increasingly heterogeneous, programming across different devices and their associated abstractions becomes more complex. Allowing researchers to write workloads in high-level languages that map to low-latency execution across diverse distributed target platforms will enable the development of key infrastructure for utility-scale quantum systems. For this, we introduce $\textit{Backline}$, a heterogeneous compilation and runtime framework built within PennyLane and Catalyst. Backline allows us to design and build quantum-classical workloads for high-performance and low-latency devices, with compilation directly from a Python interface through MLIR. We demonstrate the compilation and execution of several quantum workloads with low-latency data movement across a mix of CPUs, GPUs, and FPGAs, for both local and distributed remote hardware targets, all from a vendor-agnostic Python frontend. With an AMD VPK120 FPGA board as the controller, issuing each round from its hardware-handshake engine, we measured median steady-state round-trip latencies over RoCE v2 of $2.305~\mu$s to an AMD Ryzen Threadripper PRO CPU and $4.5~\mu$s to an AMD Instinct MI210 GPU across $10^6-1$ rounds per path, demonstrating microsecond-scale synchronous co-processing.
