Mark Deutel

Fraunhofer Institute for Integrated Circuits IIS

Papers on Lattice

Total citations

Topics

Publication activitypapers/week, last 8 weeks

Research focus

Architecture Design (Transformers, SSMs, MoE) (3)Training Efficiency & Optimization (3)Inference & Quantization (2)Distributed Systems & Hardware (1)

Frequent co-authors

Axel Plinge (3)Jakob Schubert (1)Maximilian Kasper (1)Maximilian Linke (1)

Papers (3)

Aug 4, 2026

3w ago·also Friedrich-Alexander-Universität, Ruhr University Bochum (RUB), Technical University of Applied Sciences, University of Technology Nürnberg (UTN)

Design-Time Optimization of Deep Neural Networks for Intermittent Learning on Microcontrollers

Energy-aware DNN design can now be optimized offline, paving the way for truly autonomous AI on intermittent power sources.

Jakob Schubert, Maximilian Kasper, Maximilian Linke +5

Architecture Design (Transformers, SSMs, MoE)Training Efficiency & Optimization

Jun 22, 2026

Efficient Network Inference via Hardware-Aware Architecture Search, Model Pruning & Quantization

Combining advanced model compression with hardware-aware architecture search can drastically enhance real-time GNSS interference monitoring on low-resource devices.

Lucas Heublein, Mark Deutel, Axel Plinge +1

Architecture Design (Transformers, SSMs, MoE)Distributed Systems & Hardware Inference & Quantization+1

Mar 16, 2026

PrototypeNAS: Rapid Design of Deep Neural Networks for Microcontroller Units

Forget training from scratch: PrototypeNAS finds deployable MCU-optimized DNNs in minutes using zero-shot proxies and smart search space design.

Mark Deutel, Simon Geis, Axel Plinge

Architecture Design (Transformers, SSMs, MoE)Inference & Quantization Training Efficiency & Optimization