Adri'an Castell'o

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Publication activitypapers/week, last 8 weeks

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Architecture Design (Transformers, SSMs, MoE) (1)Code Generation & Program Synthesis (1)Distributed Systems & Hardware (1)

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Jie Lei (1)H. Mart'inez (1)Héctor Martínez (1)Adrián Castelló (1)

Papers (1)

Mar 18, 2026

Jie Lei +42w ago

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings

Achieve up to 2.4x speedup over OpenBLAS on RISC-V by using MLIR and xDSL to generate optimized RVV code, finally unlocking the potential of RISC-V vector extensions.

Jie Lei, H. Mart'inez, Héctor Martínez +2

Architecture Design (Transformers, SSMs, MoE)Code Generation & Program Synthesis Distributed Systems & Hardware

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Adri'an Castell'o

Publication activitypapers/week, last 8 weeks

Research focus

Frequent co-authors

Papers (1)