Track papers across labs, topics, and trends.
Search papers, labs, and topics across Lattice.
This paper presents a hardware implementation of semi-empirical electronic structure methods, specifically Extended Hückel Theory (EHT) and non-self-consistent Density Functional Tight Binding (DFTB0), on a field-programmable gate array (FPGA). By implementing Hamiltonian construction and diagonalization directly on the FPGA using a streaming dataflow architecture, the design achieves deterministic execution and eliminates host intervention. The FPGA-based DFTB0 Hamiltonian generator demonstrates a greater than fourfold throughput improvement compared to a server-class CPU on a mid-range Artix-7 FPGA, highlighting the potential for significant acceleration.
Achieve a 4x speedup in DFTB0 Hamiltonian generation by implementing semi-empirical electronic structure theory directly on an FPGA, paving the way for sustainable, hardware-native acceleration of quantum chemistry calculations.
High-throughput quantum-chemical calculations underpin modern molecular modelling, materials discovery, and machine-learning workflows, yet even semi-empirical methods become restrictive when many molecules must be evaluated. Here we report the first hardware-native realisation of semi-empirical electronic structure theory on a field-programmable gate array (FPGA), implementing as a proof of principle Extended H\"uckel Theory (EHT) and non-self-consistent Density Functional Tight Binding (DFTB0). Our design performs Hamiltonian construction and diagonalisation on the FPGA device through a streaming dataflow, enabling deterministic execution without host intervention. On a mid-range Artix-7 FPGA, the DFTB0 Hamiltonian generator delivers a throughput over fourfold higher than that of a contemporary server-class CPU. Improvements in eigensolver design, memory capacity, and extensions to nuclear gradients and excited states could further expand capability. Combined with the inherent energy efficiency of FPGA dataflow, this work opens a pathway towards sustainable, hardware-native acceleration of electronic-structure simulation and direct hardware implementations of a broad class of methods.