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3D NAND flash, critical for AI workloads, faces scaling limits due to fundamental charge storage physics like lateral migration and coupling, which collectively reduce operating margins. Sustaining future kilolayer NAND scaling necessitates moving beyond monolithic roadmaps towards application-specific co-optimization. This includes exploring complementary solutions like ferroelectric storage and alternative channel materials for distinct data-centric computing tiers.
The physics of charge storage, not process integration, now dictates 3D NAND scaling limits, demanding a shift to application-specific co-optimization.
3D NAND flash has become the foundational non-volatile storage platform of the AI era, underpinning workloads from model training to large-scale inference and cold data archival. With roadmaps now targeting kilolayer stacks and tens of trillions of devices per die, scaling is no longer governed primarily by process integration or lithography. Instead, it is increasingly constrained by the physics of charge storage itself: lateral charge migration, electrostatic coupling, read disturb, and transport limitations are entering a margin-limited regime. In this regime, their collective interaction, not any single mechanism, compresses operating margins with each generation. In this Perspective, we examine these converging bottlenecks and argue that sustaining NAND scaling will require application-specific co-optimization rather than a monolithic device roadmap. In this framework, conventional charge-trap flash, ferroelectric storage, alternative channel materials, and system-level integration are best viewed as complementary solutions targeted to distinct tiers of data-centric computing.
