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ATLAAS is presented as an MLIR-based pipeline that automatically extracts tensor-level ISA specifications from RTL-extracted accelerator semantics. It lifts bit-level LLVM IR through an 8-pass semantic lifting process, recovering high-level tensor structures and data layout transformations. Evaluated on Gemmini and VTA processors, ATLAAS generates specifications that enable automatic software stack generation, revealing previously undocumented hardware features and facilitating compiler backend development.
Automating tensor ISA extraction from RTL slashes the engineering effort required to build complete software stacks for novel accelerators, even revealing undocumented hardware features.
Numerous tensor accelerator designs have been proposed, yet most lack well-documented ISAs and compiler backends, limiting evaluation to a handful of operators. Recent work has shown that given a tensor-level ISA specification, complete software stacks including compiler backends can be automatically generated--but writing such specifications remains a manual, expert-driven process. We present ATLAAS, the first end-to-end MLIR-based pipeline that lifts RTL-extracted accelerator semantics to tensor ISA specifications. Starting from bit-level LLVM IR produced by prior architecture-level model extraction, ATLAAS applies an 8-pass semantic lifting pipeline that progressively recovers high-level tensor structure--MAC idioms, saturation semantics, multi-dimensional buffer organizations, and data layout transformations--emitting specifications that immediately enable automatic software stack generation through the ACT ecosystem. We evaluate ATLAAS on the Gemmini systolic-array accelerator, where the pipeline collapses bit-level MLIR by up to 92.9% on processing elements and 24-34% on controller modules. ATLAAS discovers hardware features omitted from the hand-written reference, with correctness validated via Z3 SMT equivalence proofs. Generality is confirmed on TVM's VTA processor, where the same pipeline lifts all four datapath modules without accelerator-specific changes, enabling an automated path from RTL to a performance-competitive compiler backend.