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This paper addresses the challenge of unreliable read/write operations in Antiferromagnetic Tunnel Junction (AFMTJ) memories due to their ultrafast dynamics and low tunnel magnetoresistance (TMR). They propose a device-circuit co-design approach, specifically an asymmetric pulse driver (PD) for write operations and a self-timed sense amplifier (STSA) with dynamic trip-point tuning for read operations. Simulation results demonstrate improved read/write yield under process, voltage, and temperature (PVT) variations and 3D integration parasitics compared to standard MRAM front-ends, while preserving AFMTJ latency and energy benefits.
Overcome the unreliability of state-of-the-art MRAM interfaces for Antiferromagnetic Tunnel Junctions (AFMTJs) with a device-circuit co-design that achieves robust read/write yield under realistic conditions.
Antiferromagnetic Tunnel Junctions (AFMTJs) offer picosecond switching and high integration density for in-memory computing, but their ultrafast dynamics and low tunnel magnetoresistance (TMR) make state-of-the-art MRAM interfaces unreliable. This work develops a device-circuit co-designed read/write interface optimized for AFMTJ behavior. Using a calibrated SPICE AFMTJ model as a baseline, we identify the limitations of conventional drivers and propose an asymmetric pulse driver (PD) for deterministic picosecond switching and a self-timed sense amplifier (STSA) with dynamic trip-point tuning for low-TMR sensing. Our experiments using SPICE and Monte Carlo evaluations demonstrate that the proposed circuits preserve AFMTJ latency and energy benefits while achieving robust read/write yield under realistic PVT and 3D integration parasitics, outperforming standard MRAM front-ends under the same conditions.