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This paper introduces MiLSD, a micro line-segment detector designed specifically for resource-constrained devices, achieving significant improvements in accuracy while adhering to a sub-megabyte memory budget. By systematically comparing three output representations within a compact fully-convolutional architecture, the study reveals that the F-Clip center-with-length-and-angle formulation is particularly effective for small models. The findings demonstrate that while 8-bit quantization maintains performance, 4-bit quantization leads to substantial degradation, underscoring the importance of quantization-aware training for optimizing model efficiency without sacrificing accuracy.
MiLSD achieves a remarkable increase in line-segment detection accuracy on low-cost devices, outperforming previous models while fitting within a stringent memory budget.
Line segment detection is a key building block in visual SLAM, 3D reconstruction, and industrial inspection. Recent deep learning methods have greatly improved accuracy, yet even the smallest models require several megabytes of memory, exceeding low-cost MCU capacity. This work investigates the maximum achievable accuracy under a sub-megabyte budget. We propose MiLSD, a detector tailored for MCU-level constraints, and systematically compare three output representations within a compact fully-convolutional backbone. Our study shows that the proposed F-Clip center-with-length-and-angle formulation learns most effectively at small model sizes. We find that 8-bit quantization preserves full-precision performance, while 4-bit quantization causes significant degradation, particularly in angle regression, with quantization-aware training recovering only part of the loss. With a one-megabyte activation budget and inference enhancements including sub-pixel decoding, test-time augmentation, and a lightweight verifier, MiLSD improves sAP10 on ShanghaiTech Wireframe from 10.6 (25k parameters, 0.25 MB) to 24.1 within 1 MB. Rather than competing with GPU-scale parsers, we map the accuracy memory trade-off across representations, bit-widths, capacities, and post-processing strategies for embedded vision systems.