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This paper introduces a hardware annealing algorithm for Ising machines that leverages Langevin dynamics to overcome the challenge of local minima in combinatorial optimization problems. By incorporating stochastic perturbations, the algorithm enhances the probability of reaching the ground state to 86.5% and improves solution quality by 97.5% compared to existing methods. Chip-level simulations using 65-nm CMOS technology validate the algorithm's efficacy, demonstrating a 50% reduction in time-to-solution alongside superior performance metrics.
Achieving an 86.5% probability of reaching the ground state, this novel annealing algorithm outperforms existing methods by 97.5% in solution quality while halving the time-to-solution.
Ising machines are non-von Neumann machines designed to solve combinatorial optimization problems (COP) by searching for the ground state, or the lowest energy configuration, within the Ising model. However, Ising machines often face the challenges of getting trapped in local minima due to the complex energy landscapes. Hardware annealing algorithms help mitigate this issue by using a probabilistic approach to steer the system toward the ground state. In this paper, we present a hardware annealing algorithm for Ising machines based on Langevin dynamics, a stochastic perturbation by random noise. Theoretical analysis, system-level design, and detailed circuit design are carried out. We evaluate the performance of the algorithm through chip-level simulation using a standard 65-nm CMOS technology to demonstrate the algorithm's efficacy. The results show that the proposed hardware annealing algorithm effectively guides the system to reach the ground state with a probability of 86.5%, significantly improving the solution quality by 97.5%. Further, we compare the algorithm with state-of-the-art hardware annealing methods through behavioral-level simulations, highlighting its improved solution quality alongside a 50% reduction in time- to-solution.